In a nonvolatile semiconductor storage device for storing data, there are various types of data storage format in a memory cell. Among them, a phase change memory is a nonvolatile memory using a phase change film.
The phase change memory is a nonvolatile memory in which memory information is written by changing a crystalline state of a storage element in accordance with Joule heat by the current flowing through the storage element itself. Since a recording layer is once melted by applying heat of higher than 600° C. by Joule heat when forming a noncrystalline (amorphous) state, the writing current tends to be large, and a resistance value changes by two to three orders of magnitude in accordance with the crystalline state. Since this memory uses a resistance value as a signal, a read signal is large and a sense operation is easy.
The phase change memory is described in, for example, U.S. Pat. No. 5,883,827 (Patent Document 1) and others.
According to the configuration of the phase change memory in FIG. 12 of the U.S. Pat. No. 5,883,827 (Patent Document 1), the phase change memory comprises a memory array, a row (row) decoder XDEC, a bit (column) decoder YDEC, a read circuit RC, and a write circuit WC. The memory array is formed by disposing memory cells MCpr at respective intersections of word lines WLp (p=1, . . . , n) and data lines DLr (r=1, . . . , m). Each of the memory cells is configured by inserting a storage element R and a select transistor QM connected in series between a bit line DL and a ground potential. The word line WL is connected to a gate of the select transistor and a bit select line YSr (r=1, . . . , m) is connected to a corresponding bit select switch QAr, respectively.
In the configuration as mentioned above, when the select transistor on the word line selected by the row decoder XDEC enters the conduction state and the bit select switch corresponding to the bit select line selected by the bit decoder YDEC enters the conduction state, a current path is formed in the select memory cell, and a read signal is generated to a common bit line I/O. Since the resistance value in the select memory cell differs depending on the memory information, the voltage output to the common bit line I/O differs depending on the memory information. By specifying the difference by the read circuit RC, the memory information of the select memory cell is read.
The phase change memory uses a chalcogenide material such as a Ge—Sb—Te based material containing at least antimony (Sb), germanium (Ge) and tellurium (Te) as a material of a recording layer (phase change layer). Also, the characteristics of the phase change memory using the chalcogenide material have been reported (for example, Non-Patent Document 1).    Patent Document 1: U.S. Pat. No. 5,883,827    Non-Patent Document 1: IEEE International Electron Devices meeting, TECHNICAL DIGEST, USA, 2001, pp. 803-806